Frequency dividers receive an input signal X of the input frequency f.sub.X and generate an output signal Y of the output frequency f.sub.Y =f.sub.X /N, most of them with an integer division ratio N. Usually, frequency dividers are implemented as T-flip-flops or blocks with digital logic elements, such as inverters, AND-gates, OR-gates, transfer gates and the like. Such logic elements inherently exhibit delay. For example, an inverter transfer signals with a delay time t.sub.D. If t.sub.D is significantly shorter than the binary states change of an incoming signal (e.g., t.sub.D &lt;1/f.sub.X), than t.sub.D can be neglected. However, if t.sub.D is in the range of the input signal X (e.g., t.sub.D .apprxeq.1/f.sub.X), the output signal Y can come too late and can be unreliable.
The delay time t.sub.D and therefore the speed of any frequency divider is influenced by many factors, such as, for example, the carrier flight time, the charging time of capacities, propagation delay, and contention. The speed depends therefore on the manufacturing technology and on the circuit design. For example, the speed of a present day CMOS frequency divider using a T-flip-flop is limited to about f.sub.X =500-600 MHz. For higher frequencies, other technologies, such as, e.g., BiCMOS or ECL are often used. For modern telecom applications, there is the need to integrate frequency dividers into CMOS signal processing chips. To save costs, the frequency divider should be designed in the same technology as the rest of the chip and additional manufacturing steps should be avoided.
Examples of prior art approaches are described in:
1! U.S. Pat. No. 5,175,752--Yokomizo;
2! Published Application JP-5-347554--Mon;
3! Craninckx et. al.: A 1.75 GHz/3V Dual-Modulus Divide-by-128/129 Prescaler in 0.7-.mu.m CMOS, IEEE Journal of Solid-State Circuits, V.31, No.7, July 1996;
4! Rogenmoser, R., et. al.: A 1.16 GHz dual modulus 1.2-.mu.m CMOS prescaler, Proc. IEEE 1993 Custom Integrated Circuits Conf., San Diego, May 1993, pp. 27.6.1-4;
5! Foroudi, N., and Kwasniewski, T.: CMOS High-Speed Dual-Modus Frequency Divider for RF Frequency Synthesis, IEEE Journal of Solid-State Circuits, v. 30, No. 2, 02/1995; and
6! Rogenmoser, R., et. al.: 1.57 GHz Asynchronous and 1.4 GHz Dual-Modulus 1.2-.mu.m CMOS prescalers, IEEE 1994 Custom Integrated Circuits conference.
FIG. 1 shows a master-slave arrangement of prior art frequency divider 99 (hereinafter T-FF 99). FIG. 1 is a combination of FIGS. 1A-B of reference 2!. T-FF 99 has a master side (in FIG. 1 left) and a slave side (right) which receive input signal X and inverted input signal X. The underlining of the symbol indicates the inversion. On the master side, the input of inverter 1 is coupled to the output of inverter 2 (inverted outputs are denoted with a circle). The output of inverter 2 is coupled to the input of inverter 1. PMOS 3 is coupled between the input of inverter 1 and high supply line VDD. PMOS 3 is gated by input signal X. NMOS 4 and NMOS 6 are serially coupled between input of inverter 1 and low supply line VSS. NMOS 6 is gated by inverted input signal X. NMOS 4 is gated by signal Q from the slave side. PMOS 9 is coupled between the input of inverter 2 and high supply line VDD. PMOS 9 is gated by input signal X. NMOS 8 is coupled between input of inverter 2 and NMOS 6. NMOS 8 is gated by signal Q from the slave side. On the slave side (FIG. 1 right), the inputs and outputs of inverter 10 and inverter 11 are cross-coupled. PMOS 12 is coupled between in input of inverter 10 and high supply line VDD. PMOS 12 is gated by inverted input signal X. NMOS 13 and NMOS 16 are serially coupled between the input of inverter 10 and low supply line VSS. NMOS 16 is gated by input signal X. The gate of NMOS 13 is coupled to the output of inverter 2 of the master side. PMOS 14 is coupled between the input of inverter 11 and high supply line VDD. PMOS 14 is gated by inverted input signal X. NMOS 15 is coupled between output of inverter 10 and NMOS 16 and gated by the output of inverter 1 of the master side.
Signals Q and Q (inverted Q) are available at the inputs of inverter 10 and 11, respectively. T-FF 99 divides the input frequency f.sub.X of input signal X to output frequency f.sub.Y of signals Q and Q by N=2: that is f.sub.Y =f.sub.X /2. It is a drawback of prior art T-FF 99 that the input signal is supplied in a not-inverted (X) and in an inverted form (X). The inverter which is required to obtain X causes a delay limiting the maximum input frequency f.sub.X.
Reference 4! shows a dynamic frequency divider circuit having a true-single phase clock input (see 4!, FIGS. 2A-B). The frequency divider of reference 3! is a master-slave arrangement in a standard ECL-D-flip-flops arrangement which was implemented in CMOS (see 3!, FIGS. 6A-B). Both the master and the slave receive the input signal and the inverted input signal. The frequency divider in 1! comprises a D-type flip-flop receiving the input signal, a D-type flip-flop receiving the inverted input signal and an additional gating circuit at the output to speed up operation. The frequency dividers known in the art required either an inverted clock input or a full swing input signal for operation.
Accordingly, there is an ongoing need to provide an improved frequency divider and method which overcomes some or all of the deficiencies of the prior art.